In operation of a typical monitor, image signals are first sampled and scaled, the processed image signals are received by a display card of the monitor, and the display card controls voltages in a display panel of the monitor accordingly so that images can be displayed on a screen of the monitor. Nowadays, liquid crystal display monitors are widely used, and these monitors can display digital image signals. Liquid crystal display monitors can be divided into various categories of products according to their display (screen) resolution. For example, an SVGA (super video graphics array) monitor has a display resolution of 800×600 pixels, an XGA (extended graphics array) monitor has a display resolution of 1024×768 pixels, and an SXGA (super extended graphics array) monitor has a display resolution of 1028×1024 pixels.
Referring to FIG. 2, a conventional monitor 10 includes a microcomputer 11, a Phase Locked Loop (PLL) 12, an A/D (analog/digital) converter 13, and a scaler 14. The microcomputer 11 is provided for determining an image display mode according to a frequency of a horizontal synchronization (H-sync) signal and a vertical synchronization (V-sync) signal, and outputting a control signal to perform a signal processing operation according to the image display mode. The PLL 12 is provided for generating a clock phase based on the control signal output from the microcomputer 11. The A/D converter 13 is provided for sampling analog image signals to digital signals according to the clock phase provided by the PLL 12. For example, the A/D converter 13 may sample R/G/B (Red/Green/Blue) image signals transmitted from a signal source. The scaler 14 is provided for adjusting a size of the digital R/G/B signals output from the A/D converter 13 to a plurality of continuous frame units, in response to the control signal of the microcomputer 11 and by using the clock phase provided by the PLL 12. Each frame unit can be represented as a scan waveform, i.e., a clock phase having a plurality of clock pulses. The scaler 14 is also provided for outputting the adjusted digital R/G/B signals to driving circuitry (not shown) of the monitor.
Referring to FIG. 3, graph (A) shows a waveform diagram illustrating ideal operation of an input voltage of the image signals received by the scaler 14; and graph (B) shows a waveform diagram illustrating the clock phase generated by the PLL 12. The input voltage of the image signals is 0.7 volts, and an initial threshold voltage of the scaler 14 is also set at 0.7 volts. That is, when the input voltage of the image signals is greater than or equal to 0.7 volts, the scaler 14 begins to receive the clock phase provided by the PLL 12. In graph (B), the image signal is an H-sync signal that corresponds to a display resolution of 1024×768 pixels (i.e., the monitor 10 is an XGA monitor). Accordingly, a corresponding clock phase generated by the PLL 12 includes 1024 clock pulses.
However, in general, the input voltage of the image signals generates retardation. Even though the scaler 14 is set with a lower threshold voltage in order to reduce retardation, retardation in general cannot be completely avoided. Referring to FIG. 4, graph (A) shows an actual waveform diagram illustrating operation of an input voltage of the image signals received by the scaler 14; graph (B) shows an actual waveform diagram illustrating the clock phase generated by the PLL 12 according to an input voltage of ‘b’; and graph (C) shows another actual waveform diagram illustrating the clock phase generated by the PLL 12 according to an input voltage of ‘c’.
When the input voltage is greater than or equal to the threshold voltage, the scaler 14 begins to receive the clock phase provided by the PLL 12. As a result, when the input voltage is set at ‘b’, the clock phase includes 1025 clock pulses; and when the input voltage is set at ‘c’, the clock phase includes 1024 clock pulses. Therefore if the threshold voltage is improperly set, the quantity of the clock pulses varies when the input voltage generates retardation. This in turn is liable to impair the stability of the monitor and its display performance.
It is desired to provide a method for adjusting clock phase of a monitor that can overcome the above-described deficiencies.